Semiconductor device arrangement and method

ABSTRACT

A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application is a divisional application of U.S. application Ser. No. 12/036,823, filed Feb. 25, 2008, and which is incorporated herein by reference.

BACKGROUND

This disclosure relates to a semiconductor device arrangement with at least one power transistor and at least one gate resistor, the power transistor having an extremely high switching speed owing to very low device capacitances. In the turn-off process, the so-called decommutation process, however, current and voltage overlap in the power transistor. To minimize any turn-off losses resulting from this, it is possible to turn off the channel current very fast by small external gate series resistors.

Turn-off losses can also be reduced by using the output capacitance Ca as a turn-off unloading capacitor. In this process, the load current commutates completely into the output capacitance Ca. As a result, the semiconductor device suffers virtually no heat losses in the turn-off process, but only a capacitive displacement current into the output capacitance Ca with an energy content E_(Ca) of

$\begin{matrix} {{ECa} = {\int_{0}^{u_{DS}}{{Ca} \cdot U \cdot \ {\mathbb{d}U}}}} & \left( {{equation}\mspace{14mu} 1} \right) \end{matrix}$

wherein u_(DS) represents the rising drain-source voltage in the turn-off process. From this can be derived the capacitive energy content of the semiconductor device in the off state at a voltage U_(DS). This energy content can be minimized by reducing the value of the output capacitance Ca while reducing the size of the component.

In a switching process modified as described above by using the output capacitance Ca, the voltage increase during the turn-off process is however no longer controlled by the gate, but only by the load current I_(L) to be disconnected. The voltage increase du/dt is determined by the load current I_(L) in a linear manner and is inversely proportional to the output capacitance Ca with du/dt=I _(L) /Ca  (equation 2),

Wherein I_(L) represents the load current and Ca represents the output capacitance of the power transistor.

By reducing the dimensions of the device, the output capacitance Ca is reduced to a very low value, so that at high current peaks the voltage increase du/dt reaches values which may significantly exceed the permissible breakdown voltage. Owing to the intrinsic structure of the semiconductor devices, the output capacitance Ca is voltage-dependent, so that, based on the above equation 2, the value of Ca changes as du/dt increases during the turn-off process. This change causes both a change of the capacitive displacement current for the output capacitance Ca and a change of the capacitive displacement current at the gate electrode.

In a non-linear condition, i.e. if there are parasitic inductances in the drive circuit, the change of the gate current induces a reverse voltage and may result in oscillations, in particular if the exciting voltage, is amplified by the power transistor. This results in an upper limit frequency via the charge of the input capacitance of the power transistor and the through-conductivity of the power transistor. In high-voltage devices, this may be significantly lower than the inherent resonance of the serial oscillator circuit made up of the drain-gate capacitance and the gate inductance. Oscillations during the turn-off process of such power transistors are undesirable, as they affect the EMC (electromagnetic compatibility) of the power transistor.

The fast and, with the aid of the output capacitance, nearly loss-free switching of power transistors is further limited by a very high current chopping in the power circuit. If the power transistor is turned off in a completely unloaded state, the load current completely commutates into the output capacitance Ca. In this process, the gate voltage may fall below the Miller plateau at full load current and even be reduced to zero. The Miller plateau is the potential at the insulated gate which still ensures that the channel of a field effect power transistor remains open.

If the power transistor as a switch reaches the externally preset link voltage, the switch can supply the load current. The di/dt resulting from this will cause a voltage reduction at the power transistor via the existing source inductances and, if the gate potential remains constant, contribute to an effective biasing of the channel. It has however been found that, owing to the capacitive coupling between gate and source, the gate potential follows a steep voltage reduction to source, resulting on the one hand in an incomplete biasing of the channel and on the other hand in an excessively high voltage amplitude at the gate.

In combination with the gate inductances, the rapid voltage change at the gate due to the capacitive coupling between gate and source also excites undesirable oscillations. Both effects are due to the inductances existing in a power transistor between the control electrode and a switching electrode. Such inductances are built up by the conductor routing to the gate connections of the power transistor within the semiconductor device and in part by the connecting elements forming induction loops between external contacts of the semiconductor device arrangement and the internal contact surfaces on the semiconductor chip of the power transistor.

For these and other reasons, there is a need for the present invention.

SUMMARY

One embodiment provides a semiconductor device arrangement with at least one power transistor and at least one gate resistor located between a gate connection and a connecting point, wherein a further switchable element is provided between the connecting point and the source of the power transistor. There are parasitic inductances between the connecting point and the source of the power transistor. The switchable element is located between the connecting point and the source of the power transistor and at steep switching edges bridges the inductances between the connecting point and the source.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIG. 1 illustrates the principal layout of one embodiment.

FIG. 2 illustrates a Boolean truth table explaining the switching function of a switchable element.

FIG. 3 illustrates a diagrammatic cross-section through a switchable element according to one embodiment.

FIG. 4 illustrates a principal configuration according to one embodiment.

FIG. 5 illustrates is a diagrammatic cross-section through a switchable element according to one embodiment.

FIG. 6 illustrates a diagrammatic top view of the switchable element according to FIG. 5.

FIG. 7 illustrates a diagrammatic cross-section through a switchable element according to one embodiment.

FIG. 8 illustrates the principal layout of one embodiment.

FIG. 9 illustrates a principal equivalent circuit diagram of a semiconductor device arrangement according to one embodiment.

FIG. 10 illustrates a diagrammatic cross-section through a switchable element of a semiconductor device arrangement according to one embodiment.

FIG. 11 illustrates an operational amplifier as a further switchable element of one embodiment.

FIG. 12 illustrates a schematic sketch of a semiconductor device arrangement according to one embodiment.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.

FIG. 1 illustrates a principal layout of one embodiment. This circuit includes a semiconductor device arrangement 1 with a power transistor T_(H) and a gate resistor R_(G) located between a gate G of the power transistor T_(H) and a connecting point H in a drive circuit of the power transistor T_(H). A switchable element 2 is provided between the connecting point H and a source S of the power transistor T_(H). This switchable element 2 is configured such that it meets the requirements of the Boolean truth table illustrated in FIG. 2.

FIG. 2 is a Boolean truth table explaining the switching function of the switchable element 2 according to FIG. 1. The left-hand column of the Boolean truth table lists states or phases of the power transistor T_(H). The second column lists the voltage values of the connecting point H, with h being high and l being low. The third column lists the corresponding conditions at the gate G of the power transistor T_(H), likewise with h being high and l being low. The fourth column finally lists the switching states of the switchable element for a first option, wherein the switchable element is switched on both in the turn-off phase and in the off state of the power transistor T_(H). The fourth column also illustrates a second option, wherein the switchable element 2 from FIG. 1 only completes the circuit in the turn-off phase of the power transistor T_(H), connecting the connecting point H to the source S of the power transistor T_(H).

FIG. 3 is a diagrammatic cross-section through a switchable element according to one embodiment. This switchable element is suitable for option 1 of the Boolean truth table according to FIG. 2. For this purpose, the switchable element has been integrated into the body zone 7 of the power transistor T_(H) as an n-type depletion MOSFET 41.

For this purpose, a highly doped n⁺-type zone 32 is introduced into the body zone 7 of the power transistor T_(H), and this n⁺-type zone 32 is contacted by the connecting point H according to FIG. 1. Between this n⁺-type zone 32 with the contact H and an n⁺-type source zone 33 of the source S of the power transistor T_(H), a lightly doped n⁻-type near surface zone is implanted as a depletion channel 34. This near-surface zone of a depletion channel 34 is controlled by a gate G₄ at source potential of the power transistor.

With this structure according to FIG. 3, an n-type depletion MOSFET is obtained in the body zone 7 of the power transistor T_(H), which represents the switchable element 2 of FIG. 1 and corresponds to option 2 of the Boolean truth table according to FIG. 2. This function may for example be obtained by ensuring that the n-type depletion channel MOSFET has a negative threshold voltage which is less than V_(th) of the power transistor T_(H) with the configuration: source contact S₄ of the switchable element at H, gate contact G₄ of the switchable element at S of the power transistor T_(H) and drain contact D₄ of the switchable element at source potential. In this way, the depletion MOSFET switches off automatically as soon as the connecting point H exceeds the negative threshold voltage V_(th) of the depletion MOSFET 41.

When integrating the switchable element into the power transistor T_(H) according to FIG. 3, is has to be taken into account that the p-n junction between the body zone 7 of the power transistor T_(H) and the n⁺-type zone 32 contacted by the connecting point H can absorb a reverse voltage of approximately 15 V, so that the limit imposed by Zener breakdown of the p-n junction is only reached at this reverse voltage. In addition, the source S of the power transistor T_(H) contacts both the p-type body zone 7 and the n⁺-type source zone 33, while the gate electrode G₄ of the switchable element is at source potential of the power transistor T_(H).

FIG. 4 illustrates a principal configuration according to one embodiment. In this configuration, the switchable element is likewise integrated into a body zone of the power transistor and designed as a junction field effect transistor 42. With a configuration of this type, the first option of the Boolean truth table from FIG. 2 can be implemented according to column 5.

FIG. 5 is a diagrammatic cross-section through a switchable element 2 according to one embodiment. The cross-section corresponds to the embodiment illustrated in FIG. 3, but owing to a very shallow n-implantation near the surface of the body zone 7 of the power transistor T_(H), there is no need for an additional gate connection G₄ as illustrated in FIG. 3. As soon as H, during the turn-off process because of the external control component or a gate driver, converges from a positive voltage to 0 V, the lightly doped depletion channel 34 becomes conducting and H therefore stops at source potential. Conversely, the channel goes into a pinch-off state during the turn-on process, as soon as H goes to a positive voltage relative to the p-well contacted by the source. The next figure illustrates the implementation of such an integration of a switchable element as JFET 42 into the body zone 7 of the power transistor T_(H).

FIG. 6 is a diagrammatic top view of the switchable element 2 according to FIG. 5. To make the structure more clearly visible, the metallization has been omitted. This top view illustrates a section of the p-type body zone 7 of the power semiconductor, the n⁺-type source zone 33 in the upper region being bounded by a broken line. Individual contact holes 35 establish the contact with the source metallization not illustrated in the drawing, and the shallow n⁻-type implantation zone between the source zone S and the connecting point H is represented by individual strips extending from the n⁺-type zone 33 to the n⁺-type zone 32 of the connecting point H.

Contact holes 36 are also provided on the side of the connecting point H to establish a connection between the metallization of the connecting point H and the n⁺-type zone located below. The wider stripes illustrated in FIG. 6 are related to the p-type body zone 7 of the power transistor and are connected to the source metallization via further contact holes 35′. This JFET structure allows for a self-cutoff characteristic, wherein in the p-type well 7 of the body zone of the power transistor, between the source S and the connecting point H, a shallow n-type implantation is introduced which, as mentioned above, is quickly depleted by the RESURF effect of the p-type well 7 located below, as soon as the connecting point H is once again restored to a voltage which may be below the threshold voltage of the power transistor.

This n⁻-type region connecting S and H is depleted by the small lateral p-type strips connected to S as illustrated in FIG. 6. The embodiments illustrated in FIGS. 5 and 6 are subject to the condition that the n-p junction from the n⁻-type region of the connecting point H to the surrounding p-type well 7 of the power transistor has to be designed for a reverse voltage capability which corresponds at least to the maximum permissible gate voltage of the power transistor.

FIG. 7 is a diagrammatic cross-section through a switchable element 2 according to one embodiment. In this case, the switchable element 2 is integrated as JFET 42 into the gate electrode structure. For this purpose, the metallization of the connecting point H is bonded to the polysilicon of the gate supply lines through vias 37 as illustrated in FIG. 7. The gate resistor R_(G) as illustrated in FIG. 1 can be created by suitable meander structures of the polysilicon line 38. At the same time, but separate from this line to the gate resistor, the gate G₄ of a JFET structure, which is electrically connected to the source S of the power transistor T_(H), can be contacted.

For this purpose, the gate resistor R_(G) between the connecting point H and the gate G of the power transistor T_(H) is ideally designed as an integrated gate resistor. As illustrated in FIG. 7, a connection to the connecting point H is established using a gate bond, so that the gate poly located below can be contacted from this point and meander to the gate of the power transistor T_(H), from where it is routed into the gate ring and the rest of the gate electrode not illustrated in the drawing.

If a JFET 42 is to be integrated towards the source, a contact has to be established between the gate poly and the source S, which, as illustrated in FIG. 7, can be produced on a gate oxide 23 or on a field oxide 39. This however requires the separation of the gate poly around the source contacts illustrated in FIG. 6, as there would otherwise be a short circuit to the gate electrode, which would prevent the switching-on of the transistor. In other words, the source S contacts a small piece of the n-p poly material separated from the rest of the gate electrode and only connected to the rest of the n-type gate poly structure via the JFET 42.

FIG. 8 illustrates switchable elements for the implementation of option 2 in column 5 of the Boolean truth table according to FIG. 2. As the connecting point H has not only to be held at source potential in the turn-off phase of the power transistor, but this bridge also has to be maintained in the off state, an additional switching transistor T_(S) is used to take over the function of the switchable element according to FIG. 1; this may for example be installed into a control IC for the power transistor.

FIG. 8 illustrates the layout of a further one embodiment of the invention, wherein the switching transistor T_(S) is driven by an AND gate with an inverted input E1. The signals required for this purpose may for example be generated by a control IC, which offers particular advantages if the power transistor is at least partially designed as a package together with a part of the drive circuit or with the whole control IC.

FIG. 9 is an equivalent circuit diagram of a semiconductor device arrangement 1 according to one embodiment. The semiconductor device arrangement 1 includes a power transistor T_(H), which may for example be used in a half bridge circuit as a low side switch (LSS). This power transistor T_(H) has a gate connection 14 as a gate G of a semiconductor chip. Between the gate connection 14 and the connecting point H, such semiconductor device arrangements are provided with a gate resistor R_(G), across which a voltage differential builds up while the insulated gate is loaded or unloaded. The gate is loaded or unloaded via a control line 16 connecting the connecting point H to the output 17 of a driver circuit 18.

The power transistor T_(H) further includes a drain D, which may for example be at the potential to be switched, and a source S, which approximately adopts the potential to be switched as the power transistor T_(H) switches through. When the power transistor T_(H) switches off, the source S is reset to its low starting potential. Owing to a capacitive coupling between the gate G and the source S, the gate potential follows the source potential by using capacitive displacement currents, in one embodiment a turn-off phase, when the driver output 17 applies a turn-off signal ΔV to the connecting point H. In order to suppress any oscillation in this turn-off phase, a switchable element 2 is located between the connecting point H and the source S; this is controlled via a gate connection 14 and uses the voltage differential across the gate resistor R_(G) to bridge any parasitic inductances present in the main transistor T_(H) between gate and source in the turn-off phase.

As a result, the parasitic inductances are virtually short-circuited in the turn-off phase of the power transistor T_(H) and oscillations are suppressed without increasing switching losses and without affecting the switching speed of the power transistor T_(H).

For this purpose, the switchable element 2 according to one embodiment illustrated in FIG. 9 includes two n-channel MOS transistors T₁ and T₂ with body diodes B1 and B2 which block anti-serially, with the result that the parasitic inductances between the connecting point H and a source S are bridged as the gates G₁ and G₂ are triggered only in the turn-off phase at a suitable voltage differential across the gate resistor R_(G). The gates G₁ and G₂ of the transistors T₁ and T₂ are for this purpose connected to the gate G of the power transistor T_(H).

The drains D1 and D2 of the transistors T₁ and T₂ form a switching node K. The source S1 of the first transistor T₁ is connected to the connecting point H, while the source S2 of the second transistor T₂ is electrically connected to the source S of the power transistor T_(H). Any oscillations caused by parasitic inductances between the connecting point H and the source S of the power transistor T_(H) are thereby prevented. For this purpose, the connecting point H is electrically connected to the switching node K via the first body diode B1, while the source S of the power transistor T_(H) is electrically connected to the switching node K via the body diode B2 of the second transistor T₂ of the switchable element 2.

A method for the production of a semiconductor device arrangement 1 with a switchable element 2 in the drive circuit includes the following process steps. First, a power transistor T_(H) with parasitic inductances between a connecting point H and a source S and a gate resistor R_(G) between the connecting point H and a gate G of the power transistor T_(H) is provided. A switchable element 2 is then produced to bridge the inductances between the connecting point H and the source S in the turn-off phase of the power transistor at a steep switching edge ΔV. To produce a switching element 2 operating like this, a first and a second n-type channel MOSFET T₁ and T₂ are first produced in a semiconductor body 12 with a common gate G_(1,2) and a common drain D_(1,2), their first and second body diodes B₁ and B₂ being anti-serially connected to one another.

The common gate G_(1,2) can now be connected to the gate G of the power transistor T_(H), the first source S1 of the first MOSFET T₁ can be connected to the connecting point H and the second source S2 of the second MOSFET T₂ can be connected to the source S of the power transistor T_(H). If the power transistor T_(H) is a lateral FET, the first and second n-channel MOSFETs T₁ and T₂ can be monolithically integrated into the semiconductor body 12 of this FET.

In power transistors T_(H) with a vertical FET structure, a separate semiconductor device is produced as a switching element 2, its metallization 29 on the back side 4 being mounted on the source S of the power transistor T_(H) in the form of a stacked semiconductor chip 13. In this case, the switchable element 2 supports on a p-type substrate 5 the first and second n-channel MOSFETs T₁ and T₂, the common drain D_(1,2) of which, which consists of a n-type semiconductor material 8, being grown epitaxially on the substrate 5. The p-n junction 3 between the p-type substrate 5 and the n-type drain region 15 of the transistors T₁ and T₂ forms a large-area diode P_(D) connected in parallel to the second body diode B₂.

This advantageously creates a MOS device which conductively connects the connecting point H upstream of an internal or external gate resistor R_(G) to the source S of the semiconductor device arrangement 1. Ideally, the voltage drop across the gate resistor R_(G), which results from the difference between the Miller plateau and the reference voltage of the gate control, is utilized. If the switching process is completely load-free and di/dt is limited via the source inductance, this switch does not become active, because the switchable element 2 between the source S of the power transistor T_(H) and the connecting point H opens as soon as the voltage at the gate G drops below the Miller plateau. This drop below the Miller plateau occurs if the threshold voltage of the switchable element 2 equals that of the power transistor T_(H).

IA slightly lower value for the threshold voltage of the switchable element 2, can be selected in order to allow a reliable closing of the switchable element 2 at the Miller plateau. Such a configuration would noticeably pull the connecting point H upstream of the gate resistor R_(G) to source potential at the start of the turn-off process, when the input capacitance is discharged to the level of the Miller plateau. It would then remain at source potential during the entire turn-off phase without blocking an effective limitation of di/dt via the source inductance. Implementation in the semiconductor body 12 is based on the modification of the production masks, the gate structure level, the metal level and the contact hole level. At the end, only one additional level is required for masking the body contact.

In a further possible variant, the driver circuit 18 would after turn-off, i.e. when the driver output 17 switches to zero, output a further positive signal to connect the connecting point H to the source S by triggering a switchable element 2. Such a signal may remain positive for a fixed time or be held at a positive level by the actual gate characteristic. The switchable element of a corresponding semiconductor structure is illustrated in the following figure.

FIG. 10 is a diagrammatic cross-section through a switchable element 6 of a semiconductor component arrangement 6 of a semiconductor device 10 according to one embodiment. This switchable element 6 includes an n-channel field effect transistor T₃ with a channel K₃, a gate G₃, a drain D₃ and a source S₃. While the drain D₃ contacts a highly doped n⁺-type drain zone 27, the source S₃ contacts both an n⁺-type source zone 26 and a p-type base zone 31. If a positive potential is applied to G₃, the p-type base zone 31 forms an n-type channel K₃ in the p-type well 7 below the gate oxide 23. The p-type well 7 is insulated against the surrounding n-type semiconductor material 8 of the switchable element 6 via a body diode B₃ of a p-n junction 3.

To create a temporary short-circuit between the connecting point H of a power transistor and its source as illustrated in FIG. 1 in the turn-off phase of the power transistor, a positive signal is applied to the gate G₃ of the switchable element 6. For this purpose, the drain D₃ of the power transistor T_(H) is electrically connected to the connecting point, while the source S₃ is connected to the source S of the power transistor T_(H).

As explained above, the driver circuit of the power transistor T_(H) has, to achieve this, to output a further positive signal in the turn-off phase, which is connected to the gate G₃ with the switchable element 6 illustrated in FIG. 4. Such a switchable element 6 in the driver circuit of the power transistor T_(H) can be located monolithically on the semiconductor chip of the power transistor, monolithic integration being possible both for lateral MOSFETs and for vertical MOSFETs.

The gate G₃ is externally accessible, a complementary driver pulse controlling the gate G₃ such that the switchable element 6 for the semiconductor device arrangement 10 bridges the inductances between the connecting point H and the source of the power transistor T_(H) at a steep switching edge. For this purpose, a p-type well 7 of the switchable element 6 is provided in an n-type semiconductor material 8 of the semiconductor body 12 of the semiconductor chip 13.

After such a MOSFET T3 has been produced in a semiconductor body 12, its drain D₃ is electrically connected to the connecting point H of the power transistor, its source S₃ to the source S of the power transistor T_(H) and its gate G₃ to a driver output which supplies a complementary switching signal if there is a steep turn-off edge at the gate G.

In one embodiment, the voltage differential across the gate resistor R_(G) between the gate and the connecting point H is evaluated by an operational amplifier 11 acting as a switchable element 9 as illustrated in FIG. 11. The operational amplifier 11 generates an amplified signal if the potential at the gate is higher than at the connecting point H. This occurs whenever the power transistor is in a turn-off phase. The operational amplifier 11 then outputs a positive amplified signal at its output A, wherein a structure according to FIG. 4 can once again be connected to the output A. This signal is used to connect the connecting point H to the source S of the power transistor T_(H) illustrated in FIG. 1. For this purpose, the operational amplifier 11 may either be mounted as a semiconductor device on the semiconductor chip or fitted to the semiconductor chip of the control IC.

FIG. 12 is a schematic diagram of a semiconductor device arrangement 20 according to one embodiment. Components of the same function as in the preceding figures are identified by the same reference numbers and not explained again. In this embodiment of the invention, an operational amplifier 11 as briefly mentioned above is used to utilize the voltage differential across the gate resistor R_(G) and apply it to the inputs E₁ and E₂ of the operational amplifier 11. For this purpose, the connecting point H is connected to the first input E₁ of the operational amplifier 11 and the gate G of the power transistor T_(H) is connected to the second input E2 of the operational amplifier 11.

The amplified output signal A is used to drive the gate G₃ as illustrated in FIG. 4 and to connect the connecting point H of the power transistor T_(H) to the source S of the power transistor T_(H), thus short-circuiting all inductances between the connecting point H and the source S of the power transistor T_(H) in the turn-off phase of the power transistor T_(H). For this purpose, the connecting point H is connected to the drain D₃ of the transistor T₃ and the source S of the power transistor T_(H) is connected to the source S₃ of the transistor T₃ of the switchable element 6.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof. 

What is claimed is:
 1. A semiconductor device comprising: at least one power transistor; at least one gate resistor located between a gate of the power transistor and a connecting point in a drive circuit of the power transistor; and a switchable element provided between the connecting point and a source of the power transistor, wherein the switchable element is monolithically integrated into the power transistor.
 2. The semiconductor device of claim 1, wherein the switchable element is a depletion MOSFET with its own gate connection, which is monolithically integrated into a body zone of the power transistor, wherein the gate connection of the MOSFET is electrically connected to the source of the power transistor.
 3. The semiconductor device of claim 2, wherein the drive point forms a source of the depletion MOSFET and the source of the power transistor forms a drain of the depletion MOSFET and the gate contact of the depletion MOSFET is electrically connected to the source of the power transistor.
 4. The semiconductor device of claim 1, wherein the switchable element is a junction field effect transistor monolithically integrated into a body zone of the power transistor, its channel zone being represented by a shallow n-implantation, and wherein the channel zone can be depleted from the p-type region of the body zone.
 5. The semiconductor device of claim 1, wherein the switchable element is a junction field effect transistor structure integrated into the gate structure of the power transistor.
 6. The semiconductor device of claim 1, wherein the switchable element is a switching transistor driven by an AND gate with an inverted input, and wherein the output of the AND gate is electrically connected to the gate of the switching transistor.
 7. A semiconductor device arrangement comprising: a power transistor having a gate; a connecting point in a drive circuit of the power transistor; a gate resistor of the power transistor located between the connecting point and the gate; and a switchable element located between the connecting point and a source of the power transistor and connected to the gate such that the parasitic inductances between the connecting point and the source are bridged in the turn-off phase of the power transistor at steep switching edges, wherein the switchable element is monolithically integrated into the power transistor.
 8. The semiconductor device arrangement of claim 7, wherein the switchable element includes two transistors, having body zones that are arranged such that they block anti-serially.
 9. The semiconductor device arrangement of claim 8, wherein the two transistors have a common gate electrically connected to the gate of the power transistor.
 10. The semiconductor device arrangement of claim 8, wherein the two transistors have drains that form a switching node.
 11. The semiconductor device arrangement of claim 7, wherein the switchable element is installed as a monolithically integrated component into a lateral field effect power transistor.
 12. The semiconductor device arrangement of claim 7, wherein: the power transistor has a body zone; and the switchable element is monolithically integrated into the body zone.
 13. The semiconductor device arrangement of claim 12, wherein the body zone includes: a highly doped n⁺-type zone that is contacted by the connecting point; an n⁺-type source zone spaced apart from the highly doped n⁺-type zone contacted by the connecting point forming the source of the power transistor; and a lightly doped n⁻-type near surface zone implanted as a depletion channel and being controlled by a gate terminal of the switchable element connected to the source of the power transistor.
 14. The semiconductor device arrangement of claim 12, wherein: the switchable element includes a gate electrode; the connecting point is bonded to a polysilicon gate supply line connected to the gate electrode of the switchable element; and the gate electrode of the switchable element is electrically connected to the source of the power transistor.
 15. The semiconductor device arrangement of claim 14, wherein the gate resistor is formed by a meander structure of the polysilicon gate supply line.
 16. A method for the production of a semiconductor device arrangement with a switchable element in the drive circuit, comprising: providing a power transistor with parasitic inductances between a connecting point and a source and with a gate resistor between the connecting point and the gate; monolithically integrating a switchable element into the power transistor, wherein the switchable element, at a steep switching edge, bridges the inductances between the connecting point and the source in a turn-off phase of the power transistor.
 17. The method of claim 16, wherein a first and a second n-channel MOSFET are first produced in a semiconductor body with a common gate and a common drain, their first and second body diodes being connected back to back.
 18. The method according to of claim 17, further comprising: connecting the common gate to the gate of the power transistor; connecting the first source of the first MOSFET to the connecting point; and connecting the second source of the second MOSFET to the gate of the power transistor.
 19. The method according to of claim 16, further comprising: providing a lateral FET as a power transistor; and monolithically integrating the first and second n-channel MOSFETs into the semiconductor body of the FET. 